Simulating a Pipelined CPU Open Access

Bush, Aaron Lee (2010)

Permanent URL: https://etd.library.emory.edu/concern/etds/ht24wj87k?locale=en
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Abstract

The CS355 course in Computer Architecture teaches both entry-level and advanced pipelined CPU technology. For most of the computer components discussed in lectures, the course uses a circuit simulation program that allows students to gain an interactive experience with basic computer technology. However, the course has always lacked a simulation program for the pipelined CPU. Due to the complex nature of pipelining and the success with using the simulation software for other circuits, we have developed two versions of the pipelined CPU using the simulation program. By offering students a hands-on understanding of instruction pipelining, our simulated processors will greatly enhance the course.

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Background Information . . . . . . . . . . . . . . . . . . 2
2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Logic-Sim . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Theory of Pipelining . . . . . . . . . . . . . . . . . . . . . 6
3 The Basic Pipelined CPU . . . . . . . . . . . . . . . . . . . 10
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Instruction Encoding . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Branch Instructions . . . . . . . . . . . . . . . . . . . 14
3.2.2 Non-Branch Instructions . . . . . . . . . . . . . . . . 18
3.3 Instruction Fetch (IF) Stage . . . . . . . . . . . . . . . 23
3.4 Instruction Decode (ID) Stage . . . . . . . . . . . . . 27
3.5 Execution (EX) Stage . . . . . . . . . . . . . . . . . . . 31
3.5.1 Selecting the Correct Operands for the ALU . . . 35
3.5.2 The Program Status Register (PSR) . . . . . . . . . 38
3.6 Memory (MEM) Stage . . . . . . . . . . . . . . . . . . . 39
3.6.1 Branch Decision Circuit . . . . . . . . . . . . . . . . . 42
3.7 Write Back (WR) Stage . . . . . . . . . . . . . . . . . . 44
3.8 Stalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9 The Basic Pipelined CPU in Logic-Sim . . . . . . . . . 48
4 The Advanced Pipelined CPU . . . . . . . . . . . . . . . . 51
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2 Read after Write Data Hazard in ALU Instructions . 53
4.2.1 Solving the Data Hazard in ALU Instructions . . . 59
4.3 Read after Write Data Hazard in LD Instructions . . 60
4.3.1 Solving the Data Hazard in LD Instructions . . . . 65
4.4 Control Hazard in Branch Instructions . . . . . . . . . 67
4.4.1 Reducing the Branch Delay . . . . . . . . . . . . . . . 68
4.5 The Advanced Pipelined CPU in Logic-Sim . . . . . . 69
5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . 72

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